When the dimension of a printed circuit board becomes smaller and smaller, the available surface for placing IC components becomes smaller and smaller as well. Conventionally, a plurality of IC semiconductor packages are side-by-side mounted on a printed circuit board which no longer can be implemented in advanced miniature electronic products. Therefore, in order to meet the requirements of smaller surface-mounting area and higher densities of components, 3D package is proposed by vertically stacking multiple semiconductor packages. This is also called POP (Package-On-Package) device. The most common way to vertically stacking multiple semiconductor packages is to use solder balls or an interposer substrate with solder paste on both sides thereof. If use solder balls, besides of solder joint crack issue, the solder ball size should be large enough for stack spacing that will easily cause solder bridging or contamination issue. Moreover, due to the pitch between the large solder balls, the pin counts and the trace layout are limited. The conventional POP device cannot accord with fine pitch applications in miniature electronic devices. Furthermore, because of CTE mismatching between the stacked semiconductor packages and spacer, such as solder balls or interposer substrate, the soldering joints are easily broken. The interposer substrate has an opening at the center and a plurality of PTHs disposed around the opening, the cost will increase.
A conventional semiconductor package with micro-contacts and a conventional POP device with micro-contacts are revealed in US patent application publication No. 2006/0138647 and U.S. Pat. No. 6,476,503 respectively. As shown in FIG. 1, a semiconductor POP device 100 utilizing micro-contact technology primarily comprises a first semiconductor package 110, a second semiconductor package 120, and solder paste 130 at micro-contacts where the second semiconductor package 120 is stacked on the first semiconductor package 110 and is electrically connected to each other by solder paste 130. The first semiconductor package 110 includes a first substrate 111, a first chip 112 disposed on an upper surface 111A of the substrate 111, a plurality of bumps 113 disposed on a lower surface 111B of the substrate 111, and a first encapsulant 115. The bonding pads of the first chip 112 are electrically connected to the first substrate 111 by a plurality of first bonding wires 114 passing through the first slot 111C. The first bonding wires 114 are encapsulated by the first encapsulant 115. The second semiconductor package 120 includes a second substrate 121, a second chip 122 disposed on the upper surface 121A of the substrate 121, a plurality of bumps 123 disposed on the lower surface 121B of the substrate 121 such as copper bumps or non-reflow pillar bumps, and a second encapsulant 125. The bonding pads of the second chip 122 are electrically connected to the substrate 121 by a plurality of second bonding wires 124 passing through the second slot 121C. The second bonding wires 124 are encapsulated by the second encapsulant 125. A plurality of connecting pads 111D are disposed on the upper surface 111A of the first substrate 111 of the first semiconductor package 110. The bumps 123 of the second semiconductor package 120 are connected with the corresponding connecting pads 111D of the first semiconductor package 110 by the solder paste 130 to achieve micro-contact configuration. Since the first semiconductor package 110 and the semiconductor package 120 are mechanically stacked and electrically connected by the micro contacts so that the pin counts can be increased and the available area for trace layout can also be increased, moreover, the stacking standoff of POP can be smaller. However, due to the mismatching of the welded shapes and area, the soldering strengths between the bumps 123 and the connecting pads 111D are different after reflowing the solder paste 130, especially, the reflowed solder paste 130 on the welding surface of the connecting pads 111D are planar which is weaker to shear stresses caused by thermal stresses of the first substrate 111 due to temperature variations. Furthermore, there is a layer of plated nickel/gold formed on the upper surface of the connecting pads 111D where the gold will diffuse into the solder paste 130 to form brittle gold/solder intermetallic layer which will reduce the bonding strength of the soldering interface. Therefore, as the semiconductor POP device 100 is operated under high speed or under poor thermal dissipation environment, the micro contacts will easily be broken at the interfaces between the connecting pads 111D and the solder paste 130 or at the bumps 123.